Semiconductor device package with reduced leakage
A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating in...
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Main Authors | , , , , , , |
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Format | Patent |
Language | English |
Published |
29.05.2007
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Online Access | Get full text |
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Abstract | A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface. |
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AbstractList | A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface. |
Author | Osenbach, John William Libricz, Jr, George John Carberry, Patrick Joseph Shilling, Thomas Herbert Gilbert, Jeffery John Safar, Hugo Fernando Moyer, Ralph Salvatore |
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References | Sekine et al. (2003/0057573) 20030300 Koike et al. (2004/0262741) 20041200 Hofer et al. (2004/0232435) 20041100 Liang (5378924) 19950100 Asada et al. (5091341) 19920200 Loh et al. (2005/0269587) 20051200 Alfaro et al. (5458716) 19951000 Redmond (4819041) 19890400 Karnezos et al. (6326678) 20011200 Doering et al. (5345106) 19940900 Marrs (5701034) 19971200 Kawata (2004/0232425) 20041100 Suzuki et al. (3778887) 19731200 Hochstein (6517218) 20030200 Wakefield (5362679) 19941100 Ewer et al. (6204554) 20010300 Kamada (6943433) 20050900 Harrah (6936855) 20050800 Mehringer et al. (5869883) 19990200 Jeng et al. (5783860) 19980700 Lerner et al. (5381042) 19950100 Combs (6552417) 20030400 |
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Snippet | A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead... |
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Title | Semiconductor device package with reduced leakage |
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