Systems and methods for minimizing harmonic interference
Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interferenc...
Saved in:
| Main Author | |
|---|---|
| Format | Patent |
| Language | English |
| Published |
20.02.2007
|
| Online Access | Get full text |
Cover
Loading…
| Summary: | Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interference clock having the changed duty cycle while keeping the predetermined frequency. |
|---|