Integrated circuit with improved signal noise isolation and method for improving signal noise isolation

A system-on chip (SOC) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks and ESD protected pads ( and ). A VDD isolation pad is connected to an N well ring of the first noise sensitive circuit to collect noise from the substrate and isolate the circuit f...

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Bibliographic Details
Main Authors Banerjee, Suman K, Ferrer, Enrique, Hartin, Olin L, Secareanu, Radu M
Format Patent
LanguageEnglish
Published 21.11.2006
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Summary:A system-on chip (SOC) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks and ESD protected pads ( and ). A VDD isolation pad is connected to an N well ring of the first noise sensitive circuit to collect noise from the substrate and isolate the circuit from the P well region. A ground protected pad is connected to an isolated P well of a first noise sensitive circuit. The ground pad collects noise from the isolated P well and sends it to ground. A dedicated ground isolation pad is connected to a P well ring of a second noise sensitive circuit. The dedicated ground isolation pad collects noise from the P well ring and sends it to ground. The dedicated ground isolation pad and the ground pad collect noise that would normally propagate between the first and second noise sensitive circuits and additional circuits that share the same substrate.