Pulse generation circuit and semiconductor tester that uses the pulse generation circuit

A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pa...

Full description

Saved in:
Bibliographic Details
Main Authors Shinbo, Kenichi, Oonishi, Fujio, Orihashi, Ritsurou, Fukuzaki, Masashi, Motoki, Nobuo
Format Patent
LanguageEnglish
Published 01.08.2006
Online AccessGet full text

Cover

More Information
Summary:A pulse generation circuit including a pulse formation circuit for generating normal and dummy pulses according to second delay value data, a data calculation circuit for calculating first delay value data at a timing at which the pulses are generated from the pulse formation circuit according to pattern data having information for determining whether to generate pulses from the pulse formation circuit, a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting the no-pulse-generation cycle from the first delay value data, and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit.