Analog delay locked loop having duty cycle correction circuit

An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay lo...

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Bibliographic Details
Main Authors Kim, Se-Jun, Hong, Sang-Hoon, Ko, Jae-Bum
Format Patent
LanguageEnglish
Published 18.07.2006
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Summary:An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.