Prefetching data in a computer system

A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses t...

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Bibliographic Details
Main Authors Sprangle, Eric A, Rohillah, Anwar Q
Format Patent
LanguageEnglish
Published 18.04.2006
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Summary:A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.