Minimizing transistor size in integrated circuits

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate...

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Bibliographic Details
Main Authors Sander, Craig S, Klein, Rich K, Selcuk, Asim A, Kepler, Nicholas J, Spence, Christoper A, Lee, Raymond T, Holst, John C, Horne, Stephen C
Format Patent
LanguageEnglish
Published 11.04.2006
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Summary:A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.