Analog delay locked loop with tracking analog-digital converter

An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generati...

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Bibliographic Details
Main Authors Kim, Se-Jun, Hong, Sang-Hoon, Ko, Jae-Bum
Format Patent
LanguageEnglish
Published 17.01.2006
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Summary:An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.