Algorithm and methodology for the polygonalization of sparse circuit schematics

An method of creating a physical layout of an integrated circuit. A schematic file is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file. The method takes advantage of constraints on the schematic design to provide t...

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Bibliographic Details
Main Authors Schmidt, Dominik J, Chun, Perry, Saito, Richard C, Chen, Eugene Y
Format Patent
LanguageEnglish
Published 07.06.2005
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Summary:An method of creating a physical layout of an integrated circuit. A schematic file is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file. The method takes advantage of constraints on the schematic design to provide the layout file quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.