Vertical nanotube transistor and process for fabricating the same

• Main Authors: Lee, Chun-Tao, Shi, Lin-Hung, Jeng, Chi-Cherng, Lin, Wen-Ti, Chen, Wei-Su
• Format: Patent
• Language: English
• Published: 14.12.2004

1. Field of the Invention A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.