Scan cell systems and methods

• Main Authors: Sabbavarapu, Anil K, Jaber, Talal K, McFarland, Grant W, Sunkerneni, Paven R, Wu, David M
• Format: Patent
• Language: English
• Published: 09.11.2004

A conventional integrated circuit (IC) may include millions of logic gates. Each of these logic gates must be properly fabricated in order for the IC to operate as designed. Testing techniques have therefore been developed to ensure that the logic gates of an IC have been properly fabricated and that the gates provide proper functioning to the IC. According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.