Method for manufacturing a reclaimable test pattern wafer for CMP applications
1. Field of the Invention In a method for manufacturing a test pattern wafer, a silicon substrate is provided. A sacrificial oxide layer is deposited over the silicon substrate, and simulated transistor structure test features are fabricated into and on the sacrificial oxide layer. Chemical mechanic...
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| Format | Patent |
| Language | English |
| Published |
26.10.2004
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| Online Access | Get full text |
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| Summary: | 1. Field of the Invention
In a method for manufacturing a test pattern wafer, a silicon substrate is provided. A sacrificial oxide layer is deposited over the silicon substrate, and simulated transistor structure test features are fabricated into and on the sacrificial oxide layer. Chemical mechanical polishing characterization is performed using the test pattern wafer which provides data for the characterization of the chemical mechanical polishing. The sacrificial oxide layer is then stripped along with the simulated transistor structure test features, allowing the silicon substrate to be reclaimed and to be used in the fabrication of subsequent test pattern wafers. |
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