Copper damascene with low-k capping layer and improved electromigration reliability

• Main Authors: Ngo, Minh van, Martin, Jeremy I, Ruelke, Hartmut
• Format: Patent
• Language: English
• Published: 28.09.2004

The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices, particularly to a method for forming reliably capped Cu or Cu alloy interconnects, such as single and dual damascene structures formed in low dielectric constant materials. The present invention is particularly applicable to high speed integrated circuits having submicron design features and high conductivity interconnects with improved electromigration resistance. The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NHdiluted with N, discontinuing the plasma and flow of NHand N, pumping out the chamber; introducing trimethylsilane, NHand He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 to about 800 . Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.