Method of determining non-accessible device I/O pin speed using on chip LFSR and MISR as data source and results analyzer respectively

The present invention relates generally to integrated circuit testing and more specifically to structural testing of integrated circuits. A novel apparatus and methods provide the capability to structural test device input/output pins which are not connected to an external tester during the testing...

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Bibliographic Details
Main Authors Ojha, Ajay, Li, Hehching Harry
Format Patent
LanguageEnglish
Published 22.06.2004
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Summary:The present invention relates generally to integrated circuit testing and more specifically to structural testing of integrated circuits. A novel apparatus and methods provide the capability to structural test device input/output pins which are not connected to an external tester during the testing process. The method does not require a new Design For Test logic block, but rather, the method modifies existing registers on the chip to function as a (Pseudo Random Pattern Generator) PRPG and a MISR (Multiple Input Signature Register). The PRPG generates input patterns. The MISR generates an output signature. PRPG and MISR are both based on LFSR (Linear Feedback Shift Register). This allows running a random pattern generated by the PRPG, testing at-speed a path from the PRPG through the I/O logic circuitry interfacing to core logic, and storing a signature pattern in the MISR. The testing will take place at native speed of the device and no connection to the pins is required externally.