Method of forming a CMOS type semiconductor device having dual gates

• Main Authors: Kim, Woo-Sik, Lee, Nae-In
• Format: Patent
• Language: English
• Published: 27.04.2004

This application relies for priority upon Korean Patent Application No. 2001-19304, filed on Apr. 11, 2001, the contents of which are herein incorporated by reference in their entirety. A method of forming a CMOS type semiconductor device having dual gate includes forming a first gate insulation layer and a first metal-containing layer sequentially on a surface of a substrate in first and second impurity type transistor regions, removing the first metal-containing layer and the first gate insulation layer in the second impurity type transistor region, forming a second gate insulation layer and a second metal-containing layer in the second impurity type transistor region, and forming first and second electrodes in the first and second impurity type transistor regions, respectively, by patterning the first and second metal-containing layers. When first and second impurities in the transistor regions are p-type and n-type impurities, respectively, a fermi level of the first metal-containing layer has an energy level similar to the valence band of the silicon layer in the first impurity type transistor region heavily doped by a p-type impurity, and a fermi level of the second metal-containing layer has an energy level similar to the conduction band of the silicon layer in the second impurity type transistor region heavily doped by an n-type impurity.