Matrix-addressable array of integrated transistor/memory structures

• Main Author: Gudesen, Hans Gude
• Format: Patent
• Language: English
• Published: 20.04.2004

The present invention concerns a matrix-addressable array of integrated transistor/memory structures, wherein the array comprises one or more layers of semiconducting material, two or more electrode layers, as well as memory material contacting electrodes in said at least two electrode layers, wherein the memory material is a polarizable dielectric material capable of exhibiting hysteresis, particularly a ferroelectric or electret material, wherein the electrodes in said at least two electrode layers in each layer are provided as continuous or interrupted parallel extended structures, wherein said at least one layer of a semiconducting material and said at least two electrode layers form field-effect transistor structures, wherein the electrodes of a first electrode layer form the source/drain electrode pairs of said field-effect transistor structures, wherein the electrodes of an adjacent second electrode layer forms the gate electrode of the field-effect transistor structures, the gate electrodes in any case are provided in a substantial orthogonal orientation relative to the electrodes of the first electrode layer. In an array of integrated transistor/memory structures the array includes one or more layers of semiconducting material, two or more electrode layers, and memory material contacting electrodes in the latter. At least one layer of a semiconducting material and two electrode layers form transistor structures such that the electrodes of the first electrode layer forms source/drain electrode pairs and those of a second electrode layer form the gate electrodes thereof. The source and drain electrodes of a single transistor/memory structure are separated by a narrow recess extending down to the semiconducting layer wherein the transistor channel is provided beneath the recess and with extremely small width, while the source and drain regions are provided beneath the respective source and drain electrodes on either side of the transistor channel. Memory material is provided in the recess and contacts the electrodes of the transistor.