Self-resetting phase locked loop

The present invention relates generally to circuits for generating event timing signals, and more particularly to phase locked loop circuits. An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequenc...

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Bibliographic Details
Main Authors Nguyen, Nhat M, Chang, Kun-Yung K
Format Patent
LanguageEnglish
Published 24.02.2004
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