Self-resetting phase locked loop
The present invention relates generally to circuits for generating event timing signals, and more particularly to phase locked loop circuits. An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequenc...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
24.02.2004
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Online Access | Get full text |
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Summary: | The present invention relates generally to circuits for generating event timing signals, and more particularly to phase locked loop circuits.
An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequency in a first operating mode and a second frequency in a second operating mode, the second frequency being determined, at least in part, by a reference clock signal. A control circuit within the integrated circuit resets the PLL circuit by selecting the first operating mode for a predetermined time interval, then selecting the second operating mode. |
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