Method and apparatus to enhance testability of logic coupled to IO buffers

1. Field of the Invention A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the firs...

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Main Authors Babella, Anthony, Udawatta, Kapila B, Uddin, Razi
Format Patent
LanguageEnglish
Published 18.11.2003
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Abstract 1. Field of the Invention A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.
AbstractList 1. Field of the Invention A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.
Author Udawatta, Kapila B
Babella, Anthony
Uddin, Razi
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References Whetsel, Jr. (5631911) 19970500
Osawa et al. (5960008) 19990900
Edler et al. (5528610) 19960600
Phillips et al. (5671234) 19970900
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Snippet 1. Field of the Invention A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a...
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Title Method and apparatus to enhance testability of logic coupled to IO buffers
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