Method and apparatus to enhance testability of logic coupled to IO buffers
1. Field of the Invention A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the firs...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English |
Published |
18.11.2003
|
Online Access | Get full text |
Cover
Loading…
Summary: | 1. Field of the Invention
A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic. |
---|