Wet etch reduction of gate widths

• Main Authors: Kanh, Babar A, Moumen, Naim, Natzle, Wesley Charles, Yu, Chienfan
• Format: Patent
• Language: English
• Published: 09.09.2003

The field of the invention is that of integrated circuit processing in the submicron range. A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the hardmask layer; the portion of the circuit that has the correct gate length is covered with a blocking mask and the hardmask in the remainder is wet-etched to reduce its dimension, after which the gate stack is etched using both gate lengths of hardmask to produce different gate lengths in different areas.