Line monitoring of negative bias temperature instabilities by hole injection methods

• Main Authors: La Rosa, Giuseppe, Guarin, Fernando J, Rauch, III, Stewart E
• Format: Patent
• Language: English
• Published: 18.02.2003

The present invention relates generally to wafer-level reliability testing of semiconductor devices and, more particularly, to accelerated metal-oxide-semiconductor field effect transistor (MOSFET) testing for negative bias temperature instability (NBTI) effects. A process for in-line testing of a metal-oxide-semiconductor field effect transistor (MOSFET) device for negative bias thermal instability (NBTI), which degrades the gate oxide of the MOSFET device. The process generally comprises four steps. First, a hole injection method is selected that produces approximately the same gate oxide degradation as the NBTI under test. Second, a correlation is established between the NBTI degradation and device shifts due to the selected hole injection degradation method. Third, an in-line procedure is developed based on the hole injection method, using the second step to relate the measured shift to NBTI. Finally, a NBTI specification is defined based on the hole injection method using the second step. The MOSFET device is preferably a p-type MOSFET device and the hole injection method is preferably a channel hot-carrier stress method.