Fabrication method for semiconductor integrated circuit device

• Main Authors: Nakabayashi, Shinichi, Abe, Hisahiko, Ota, Katsuhiro
• Format: Patent
• Language: English
• Published: 04.02.2003

This invention relates to a technique for fabricating a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique that is applicable to the fabrication of a semiconductor integrated circuit device, including the step of polishing a thin film formed on the surface of a semiconductor wafer by a chemical mechanical polishing (CMP) method. For carrying out chemical mechanical polishing while supplying a polishing slurry to a surface to be processed of individual wafers running through a mass-production process so as to suppress occurrence of microscratches by reducing the density of coagulated particles in the polishing slurry used in a chemical mechanical polishing step, the polishing slurry used is allowed to stand in a condition filled in a container for at least 30 days or over, preferably 40 days or over, and more preferably 50 days or over so that the concentration of coagulated particles having a size of 1 m or over is at 200,000 particles/0.5 cc, preferably 50,000 particles/0.5 cc, and more preferably 20,000 particles/0.5 cc.