SDRAM having posted CAS function of JEDEC standard

1. Technical Field A synchronous semiconductor memory device satisfying the CAS function requirement of JEDEC is provided. Through command input pins and address input pins, external command signals and address signals are applied. A command decoder decodes the applied command signals. A write comma...

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Bibliographic Details
Main Author La, One-gyun
Format Patent
LanguageEnglish
Published 19.11.2002
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Summary:1. Technical Field A synchronous semiconductor memory device satisfying the CAS function requirement of JEDEC is provided. Through command input pins and address input pins, external command signals and address signals are applied. A command decoder decodes the applied command signals. A write command latency control unit, a read command latency control unit, and a column address latency control unit delay a write command, a read command, and a column address signal, respectively, for a time period equal to N/2 times a clock signal cycle in response to a latency control signal. N is an integer equal to or greater than zero, and the latency control signal is activated in response to a value set in an extended mode register set.