Content addressable storage apparatus and register mapper architecture

• Main Authors: Buti, Taqi Nasser, Klim, Peter Juergen, Le, Hung Qui, McDonald, Robert Greg
• Format: Patent
• Language: English
• Published: 12.11.2002

The present invention relates generally to information processing systems and more particularly to a methodology and implementation for a high speed content addressable memory and register mapper organization. A non-conventional CAM (content addressable memory) and register mapper organization and circuit implementation is provided which allows simultaneous execution of a large number of CAM searches. All compare circuits are placed outside of the CAM in separate match arrays where the actual comparisons occur. The CAM cell contains only latches to hold the CAM stored bit of data and a multi-port MUX to update the CAM content. The CAM bits are driven to the match arrays for match generation. The structure of the CAM and search engine facilitates implementation of the register mapper as a group of custom arrays. Each array is dedicated to execute a specific function. All of the arrays are aligned and each row of an array is devoted to one register to keep current state, shadow state and controls for that register. In an exemplary embodiment, eight custom arrays are used to execute various functions of the register mapper.