Method and device for producing undercut gate for flash memory

• Main Authors: Sung, Kuo-Tung, Lee, Ray C
• Format: Patent
• Language: English
• Published: 22.10.2002

The present invention relates to the manufacture of semiconductor integrated circuits. More particularly, the invention is illustrated with regard to memory cell structures for a flash memory cell or flash E PROM or EPROM cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the present invention can be applied to a variety of embedded memory cell structures such as microprocessors ("MICROs"), microcontrollers, application specific integrated circuits ("ASICs"), and the like. A method and resulting integrated circuit device () such as a flash memory device and resulting cell. The method includes a step of providing a substrate (), which has an active region overlying a thin layer of dielectric material (). The method uses a step of forming a floating gate layer () overlying the thin layer of dielectric material (), which is commonly termed a "tunnel oxide" layer, but is not limited to such a layer or material. The floating gate layer () has novel geometric features including slant edges (), which extend to the dielectric material (). The slant edges () create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.