Semiconductor integrated circuit and method of checking memory

• Main Authors: Satou, Masayuki, Shimizu, Isao, Fukiage, Hiroshi
• Format: Patent
• Language: English
• Published: 15.10.2002

The present invention relates to a technique for diagnosing a semiconductor integrated circuit (IC) and a technique effective for application to a technique for detecting defective bits in a semiconductor memory. The present invention relates to, for example, a technique effective for use in a semiconductor integrated circuit in which a semiconductor memory, and a test circuit for the semiconductor memory, i.e., a test pattern generator for generating each test pattern are incorporated. A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.