Method and arrangement for preconditioning in a destructive read memory

• Main Authors: Fifield, John A, Hwang, Chorng-Lii, Storaska, Daniel W
• Format: Patent
• Language: English
• Published: 03.09.2002

The present invention relates to dynamic random access memories (DRAMs) including DRAMs embedded in multi-purpose integrated circuits. More specifically, the invention relates to an arrangement and method for storing data to a DRAM. An arrangement and method is disclosed which works toward shortening the machine cycle of a DRAM. A data value is written to a storage capacitor of a memory cell of the DRAM, the data value being stored in the storage capacitor as one of low state and high state. During a first wordline activation cycle, a storage capacitor is preconditioned to a preconditioned voltage level. In a subsequent wordline activation cycle, a low state or a high state is written to the storage capacitor.In an aspect of the invention, the wordline is activated in a first wordline activation cycle to begin clearing any previously stored state of the storage capacitor. This cycle may include the reading of a stored data value from the storage capacitor. Then, immediately thereafter, while maintaining the wordline activated, the storage capacitor is preconditioned to a preconditioned voltage level, as by clamping the bitline through a bitline restore device. The wordline is then deactivated. Subsequently, the wordline is activated again during a write cycle to write one of a low state and a high state to the storage capacitor to indicate a stored data value.