Transistor metal gate structure that minimizes non-planarity effects and method of formation

• Main Authors: Grant, John M, Adetutu, Olubunmi O, Musgrove, Yolanda S
• Format: Patent
• Language: English
• Published: 23.07.2002

The present invention is related to semiconductor devices and, more specifically, to a transistor metal gate structure that minimizes non-planarity effects. A metal gate structure is formed by depositing a gate dielectric, a gate electrode, a stop layer, and a metal layer within a gate trench and removing the portions of the layers that lie outside the gate trench. A first polish or etch process is used to remove a portion of the metal layer selective to the stop layer. A second polish or etch process is used to remove portions of the gate dielectric, the gate electrode, the stop layer and the metal layer which lie outside the gate trench after the first polish or etch process. The resulting structure increases the uniformity and non-planarity of the top surface of the metal gate structure.