High voltage transistor using P+ buried layer

The invention relates to the general field of high voltage bipolar transistors with particular reference to alternatives to SOI. A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The pres...

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Bibliographic Details
Main Authors Tsai, Jun-Lin, Lin, Ruey-Hsin, Hwang, Jei-Feng, Liu, Kuo-Chio
Format Patent
LanguageEnglish
Published 23.07.2002
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Summary:The invention relates to the general field of high voltage bipolar transistors with particular reference to alternatives to SOI. A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.