Shallow trench isolation formation with two source/drain masks and simplified planarization mask

• Main Authors: Bandyopadhyay, Basab, Kepler, Nick, Karlsson, Olov, Wang, Larry, Ibok, Effiong, Lyons, Christopher F
• Format: Patent
• Language: English
• Published: 30.04.2002

The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high density semiconductor devices with submicron design features and active regions isolated by shallow insulated trenches. An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.