Method and structure of high and low K buried oxide for SOI technology

1. Field of the Invention A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion,...

Full description

Saved in:
Bibliographic Details
Main Authors Gauthier, Jr., Robert J, Schepis, Dominic J, Voldman, Steven H
Format Patent
LanguageEnglish
Published 05.03.2002
Online AccessGet full text

Cover

Abstract 1. Field of the Invention A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
AbstractList 1. Field of the Invention A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
Author Schepis, Dominic J
Voldman, Steven H
Gauthier, Jr., Robert J
Author_xml – sequence: 1
  fullname: Gauthier, Jr., Robert J
– sequence: 2
  fullname: Schepis, Dominic J
– sequence: 3
  fullname: Voldman, Steven H
BookMark eNrjYmDJy89L5WRw800tychPUUjMS1EoLikqTS4pLUpVyE9TyMhMzwCL5uSXK3grJJUWZaamKORXZKakKqTlFykE-3sqlKQmZ-Tl5-SnV_IwsKYl5hSn8kJpbgYFN9cQZw_d0uKCxJLUvJLi-PSiRBBlYGZsamRpYGpMhBIAjDs1IQ
ContentType Patent
CorporateAuthor International Business Machines Corporation
CorporateAuthor_xml – name: International Business Machines Corporation
DBID EFH
DatabaseName USPTO Issued Patents
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EFH
  name: USPTO Issued Patents
  url: http://www.uspto.gov/patft/index.html
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
ExternalDocumentID 06352905
GroupedDBID EFH
ID FETCH-uspatents_grants_063529053
IEDL.DBID EFH
IngestDate Sun Mar 05 22:30:27 EST 2023
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-uspatents_grants_063529053
OpenAccessLink https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6352905
ParticipantIDs uspatents_grants_06352905
PatentNumber 6352905
PublicationCentury 2000
PublicationDate 20020305
PublicationDateYYYYMMDD 2002-03-05
PublicationDate_xml – month: 03
  year: 2002
  text: 20020305
  day: 05
PublicationDecade 2000
PublicationYear 2002
References Kim (5998840) 19991200
Havemann (5789818) 19980800
Ray et al. (5858471) 19990100
Elsevier Science Ltd. Publication entitled "The Impact of MOSFET Technology evolution and Scaling on Electrostatic discharge protection," by S. Voldmanm microelectronics Reliability 38 (1998), pp. 1649-1668.
Publication entitled "CMOS-on-SOI ESD Protection Networks, " by S. Voldman et al., Reprinted from Journal of Electrostatics 42 (1998), pp. 333-350.
Jeng (5708303) 19980100
Machesney et al. (5587604) 19961200
IEEE Publications-ISSCC 99/Session 25/SOI Microprocessors and Memory/Paper WP 25.1 Partially-Depleted SOi Technology for Digital Logic, by G. Shjahidi et al., pp. 362-636; 426-427, (1999).
Morihara (5888854) 19990300
Publication entitled "Dynamic Threshold Body-and Gate-Coulped SOI ESD Protection Networks," by S. Voldman et al, Reprinted from Journal of Electrostatics 44 (1998), pp. 239-255.
Yamaguchi et al. (5777365) 19980700
Hamajima et al. (5869386) 19990200
West et al. (4733482) 19880300
Machesney et al. (5670388) 19970900
Kim (6063652) 20000500
IEEE Publication-ISSCC 99/Session 25/SOI Microprocessors and Memory/Paper WP 25.2, SOI Technology Performan and Modeling by J. Pelloie et al., pp. 364-365; 428-429, (1999).
References_xml – year: 19980800
  ident: 5789818
  contributor:
    fullname: Havemann
– year: 19990100
  ident: 5858471
  contributor:
    fullname: Ray et al.
– year: 19990200
  ident: 5869386
  contributor:
    fullname: Hamajima et al.
– year: 19880300
  ident: 4733482
  contributor:
    fullname: West et al.
– year: 19990300
  ident: 5888854
  contributor:
    fullname: Morihara
– year: 19980100
  ident: 5708303
  contributor:
    fullname: Jeng
– year: 19980700
  ident: 5777365
  contributor:
    fullname: Yamaguchi et al.
– year: 19991200
  ident: 5998840
  contributor:
    fullname: Kim
– year: 19970900
  ident: 5670388
  contributor:
    fullname: Machesney et al.
– year: 19961200
  ident: 5587604
  contributor:
    fullname: Machesney et al.
– year: 20000500
  ident: 6063652
  contributor:
    fullname: Kim
Score 2.5476654
Snippet 1. Field of the Invention A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions,...
SourceID uspatents
SourceType Open Access Repository
Title Method and structure of high and low K buried oxide for SOI technology
URI https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6352905
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5qEbQnRcXWB3PwurrZJE1yLg1RqRZU6K1kHxGhJqVJqT_f2Y0EL3qdhdnZ1zyWmW8AbqSUPl2NnEmyBizwhGSxKAomhVFhoiKeh7Z2ePY0zt6Ch0W46EHW1cJ80jNia5Klvt3W66ZyyZWk3tuDZy34s8UILC36wK5cVbme6-KODKdILJjpXsxtat80zQZwQCzIZSub-pfRSI9gf-6ox9Az5QmkM9esGSl0xxa1dbsxWBVoEYMddVXt8BGlbSKnsfr60AbJpcSX53tsuh_wU8B0-jrJWDfp8n1jk1mW_Ec4_wz6FNSbc0BFSkYGhuLDcRwowxPFtfI9EUV5GIvcG8LwTzajf8Yu4ND1K7FZUuEl9Gk55orMZiOv3Z58A39PeBc
link.rule.ids 230,309,783,805,888,64367
linkProvider USPTO
linkToPdf http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3JTsMwEB1VBbGcQIAo6xy4GhI36xmIUkpLJEDqLYodByG1SdWkKp_P2EERF7jakj1en5818wbgRggxpK2RMUFowBybCxbwomCCK-mG0rcyV8cOT6Ze_O48zdxZD-IuFmZBx4gtyZb6dl0vm8o4V9L13i48a8WftUZgqdUHNuW8yvIkL-4IOHmoxUy3CGM9Q8mieB92qRF6tJVN_Qs2ogPYTkzpIfRUeQTRxKRrRiLv2Oq2rlcKqwK1ZrApnVcbHKPQaeRyrL4-c4X0qMTXlxE23R_4MWD0-HYfs67T9GOl3VlS68e84Qn0idarU0BJ14xwFDFEL3CkskJp5XJoc9_P3IBn9gAGfzZz9k_dNewkD1H6PJqOz2HPJC_RLlPuBfRpZOqSMLQRV2Z6vgGRGnsU
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method+and+structure+of+high+and+low+K+buried+oxide+for+SOI+technology&rft.inventor=Gauthier%2C+Jr.%2C+Robert+J&rft.inventor=Schepis%2C+Dominic+J&rft.inventor=Voldman%2C+Steven+H&rft.number=6352905&rft.date=2002-03-05&rft.externalDBID=n%2Fa&rft.externalDocID=06352905