Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device

An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An...

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Main Authors Dev, Prakash, Maldei, Michael, Dobuzinsky, David, Faltermeier, Johnathan, Rupp, Thomas, Yu, Chienfan, Rengarajan, Rajesh, Benedict, John, Naeem, Munir-ud-Din
Format Patent
LanguageEnglish
Published 07.10.2004
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Summary:An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.