Edge seal for a semiconductor device

An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interle...

Full description

Saved in:
Bibliographic Details
Main Authors Agarwala, Birendra, Dalal, Hormazdyar, Liniger, Eric, Llera-Hurlburt, Diana, Nguyen, Du, Procter, Richard, Rathore, Hazara, Tian, Chunyan, Engel, Brett
Format Patent
LanguageEnglish
Published 06.05.2004
Online AccessGet full text

Cover

More Information
Summary:An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.