Method for extending the local memory address space of a processor

A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the...

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Bibliographic Details
Main Authors Revilla, Juan, Kolagotla, Ravi
Format Patent
LanguageEnglish
Published 03.07.2003
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Summary:A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.