Microprocessor with multiple low power modes and emulation apparatus for said microprocessor
A microprocessor comprises a central processing unit receiving a first clock signal, a plurality of peripherals receiving a second clock signal a first select unit for selecting the first clock signal out of a plurality of clock signals and a second select unit for selecting the second clock signal...
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| Main Author | |
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| Format | Patent |
| Language | English |
| Published |
24.04.2003
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| Online Access | Get full text |
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| Summary: | A microprocessor comprises a central processing unit receiving a first clock signal, a plurality of peripherals receiving a second clock signal a first select unit for selecting the first clock signal out of a plurality of clock signals and a second select unit for selecting the second clock signal out of the plurality of clock signals. The central processing unit comprises an execution unit which controls the select units upon execution of a low power mode instruction to select a clock signal for the central processing unit and the peripheral units. |
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