Register without restriction of number of mounted memory devices and memory module having the same

• Main Authors: Nishio, Yoji, Funaba, Seiji, Shibata, Kayoko, Sugano, Toshio, Ikeda, Hiroaki, Iizuka, Takuo, Sorimachi, Masayuki
• Format: Patent
• Language: English
• Published: 13.02.2003

First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of 1/2 of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of singals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.