Operational amplifier circuit, driving circuit, and driving method
An output of an operational amplifier circuit is set to the high impedance state in a given period including a transition between a period T 1 (positive polarity) in which a voltage level of a counter electrode VCOM becomes VC 1 and a period T 2 (negative polarity) in which VCOM becomes VC 2 . In th...
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| Main Author | |
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| Format | Patent |
| Language | English |
| Published |
05.12.2002
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| Online Access | Get full text |
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| Summary: | An output of an operational amplifier circuit is set to the high impedance state in a given period including a transition between a period T
1
(positive polarity) in which a voltage level of a counter electrode VCOM becomes VC
1
and a period T
2
(negative polarity) in which VCOM becomes VC
2
. In the period T
1
, data line is driven by a P-type operational amplifier OP
1
having a P-type driving transistor, while in the period T
2
, the data line is driven by an N-type operational amplifier OP
2
having an N-type driving transistor. By positively using a parasitic capacitance between the counter electrode and the data line, the voltage level of the data line is changed before driving. The excess charge is returned to the power source side by clamping the output of the operational amplifier circuit to a voltage range equal to or wider than a voltage range of power sources VDD and VSS. The voltage range of power sources VDD′ and VSS′ of a clamp circuit are set to be narrower than that of the power sources VDD and VSS of the operational amplifier circuit. |
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