System interconnect with minimal overhead suitable for real-time applications
A high-speed area-efficient cross bar switch architecture is embedded on a chip to provide connections between a plurality of ports such that multiple and concurrent point-to-point connections may be established between any devices connected to the cross bar. The cross bar is especially well adapted...
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| Main Authors | , , |
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| Format | Patent |
| Language | English |
| Published |
21.11.2002
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| Online Access | Get full text |
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| Summary: | A high-speed area-efficient cross bar switch architecture is embedded on a chip to provide connections between a plurality of ports such that multiple and concurrent point-to-point connections may be established between any devices connected to the cross bar. The cross bar is especially well adapted for distributed communication systems implemented as a system on chip. A protocol system ensures that high priority data flows through the cross bar ahead of lower priority data in the event that there are two or more devices concurrently attempting to send data to the same port. The protocol system also arbitrates between two or more devices concurrently attempting to send data to the same port, if data from such sending devices have equal priorities. In a distributed system, concurrency of transmitting and sending data can provide significant performance advantages, as semaphores and notifications are accomplished quickly. Data transfers experience minimal blocking and throughput degradation. No storage for data is necessary in the cross bar due to its light weight protocol for communication between devices, which also alleviates latencies. |
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