METHOD AND APPARATUS FOR EXTENDING FATIGUE LIFE OF SOLDER JOINTS SEMICONDUCTOR DEVICE
A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) ( 20 ) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are changed in pad dimension and exposed to more bal...
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| Main Authors | , , , , |
|---|---|
| Format | Patent |
| Language | English |
| Published |
01.08.2002
|
| Online Access | Get full text |
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| Summary: | A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) (
20
) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are changed in pad dimension and exposed to more ball/bump conductive material than the other more robust joints (
14
) in the IC (
20
) to create a ball (
24
) on a larger pad (
22
) that is larger than the normal sized ball (
14
). The larger balls (
24
) are formed by placing multiple smaller balls (
14
) together on a single pad (
22
) to form one larger ball (
24
) during a reflow operation. The larger ball (
24
) improves the overall IC reliability by improving the reliability of the weakest joints in the IC design. In addition, the standoff of both the larger balls (
24
) and the smaller balls (
14
) are engineered to be substantially equal. |
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