Arrangement for improving the ESD protection in a CMOS buffer
The invention relates to an arrangement for improving the ESD protection in a CMOS buffer which includes a plurality of PMOS transistors ( 31 to 37 ) and a plurality of NMOS transistors ( 41 - 47 ) which are connected in series with the PMOS transistors and have a finger width W N which is larger th...
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| Main Authors | , |
|---|---|
| Format | Patent |
| Language | English |
| Published |
20.06.2002
|
| Online Access | Get full text |
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| Summary: | The invention relates to an arrangement for improving the ESD protection in a CMOS buffer which includes a plurality of PMOS transistors (
31
to
37
) and a plurality of NMOS transistors (
41
-
47
) which are connected in series with the PMOS transistors and have a finger width W
N
which is larger than the finger width W
P
of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge. |
|---|