Method and structure for reducing power noise

Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. A...

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Bibliographic Details
Main Authors Frech, Roland, Rehm, Simone, Klink, Erich, Virag, Helmut, Winkel, Thomas-Michael, Becker, Wiren, Chamberlin, Bruce, Ma, Wai
Format Patent
LanguageEnglish
Published 28.06.2001
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Summary:Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.