Optimization of ASIC-based CFSMsFinite State-Machine (FSM)combined (CFSM)

• Published in: Logic Synthesis for VLSI-Based Combined Finite State Machines pp. 111 - 143
• Main Authors: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta
• Format: Book Chapter
• Language: English
• Published: Cham Springer International Publishing 25.11.2022
• Series: Lecture Notes in Electrical Engineering
• ISBN: 3031160266; 9783031160264
• ISSN: 1876-1100; 1876-1119
• DOI: 10.1007/978-3-031-16027-1_4

The Chapter is devoted to reduction of ASIC chip areas occupied by CFSM logic circuits. All methods are based on using the classes of PES. It starts from optimization of CFSM with optimal state assignment. The optimization is achieved due to replacement of logical conditions, encoding of collections of microoperations of both Mealy and Moore types. Next, these methods are applied for CFSMs with complete transformation of states. Also, the method of encoding of the fields of compatible microoperations is used for the hardware reductionHardware reduction. Next, these methods are used for optimisation CFSMs with partial transformation of states. The last parts of the Chapter are devoted to optimization based on expansion of code space and nonstandard representation of state codes. The examples of synthesis are given for majority of proposed CFSM models.