Incorporate power-saving methods at multiple levels in application-specific IP. -- Employ dynamic power reduction in an ASIC

When your team hands off your SoC design to the ASIC designer, you challenge the ASIC designer to meet power-reduction targets by implementing multiple power-saving techniques to the CS-IP blocks. A combination of time-to-market pressure and functional integration requirements conspire to make the A...

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Bibliographic Details
Published inEmbedded Systems Design Vol. 20; no. 9; p. 38
Main Author Viswanath, Somnath
Format Trade Publication Article
LanguageEnglish
Published Cambridge AspenCore 01.09.2007
Subjects
Cellular telephones
Embedded systems
Energy efficiency
Integrated circuits
Intellectual property
Power supply
Product design
United States
US
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Summary:When your team hands off your SoC design to the ASIC designer, you challenge the ASIC designer to meet power-reduction targets by implementing multiple power-saving techniques to the CS-IP blocks. A combination of time-to-market pressure and functional integration requirements conspire to make the ASIC designer rely heavily on proven IP to implement an SoC for the handheld market.
ISSN:1558-2493
1558-2507