Optimize the RISC/DSP combo for voice over IP

In contrast to RISC, DSP processors tend to pose complex pipelined architectures that lend themselves to efficient computation of complex DSP operations. But simple control instructions don't benefit from such architectures and may be impeded, contributing to the DSPs inefficiency as a control...

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Bibliographic Details
Published inCommunication systems design Vol. 9; no. 1; p. 30
Main Author Baghbadrani, Dariush
Format Journal Article
LanguageEnglish
Published San Francisco MultiMedia Healthcare Inc 01.01.2003
Subjects
Communications equipment
Digital signal processors
Integrated circuits
Internet telephony
RISC
Systems design
Systems integration
United States
US
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Summary:In contrast to RISC, DSP processors tend to pose complex pipelined architectures that lend themselves to efficient computation of complex DSP operations. But simple control instructions don't benefit from such architectures and may be impeded, contributing to the DSPs inefficiency as a control processor. Further inefficiency stems from the tendency of DSPs to work only with full-word-width data.
ISSN:1086-4644