Building a picture of ADC conversion efficiency

In today's fine-line CMOS processes, in principle, switching frequencies in excess of 3GHz are common place. Imagine if this inherent speed could be exploited in a mixed signal ADC design. In effect this has happened with the ΔΣ ADC. One class of such a ΔΣ modulator is especially interesting in...

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Bibliographic Details
Published inElectronics Weekly no. 2247; p. 28
Main Author Holdaway, Mark
Format Trade Publication Article
LanguageEnglish
Published Croydon Emap Limited 28.06.2006
Subjects
Architecture
Bandwidths
Consumption
Conversion
Design
Design engineering
Efficiency
Electric power
Electronics
Noise
Pipelines
United Kingdom > UK
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Summary:In today's fine-line CMOS processes, in principle, switching frequencies in excess of 3GHz are common place. Imagine if this inherent speed could be exploited in a mixed signal ADC design. In effect this has happened with the ΔΣ ADC. One class of such a ΔΣ modulator is especially interesting in this respect - the continuous time implementation (CTΔΣ).
ISSN:0013-5224