Amorphous non-volatile memory: the past and the future

• Published in: Electronic Engineering p. 67
• Format: Trade Publication Article
• Language: English
• Published: London CMP Information Ltd 25.04.2001
• Subjects: Computer memory; Crystals; Electrical engineering; Field programmable gate arrays; Heat; Integrated circuits; Licensing; Marketing agreements; Radiation; Selenium; Semiconductors; Silicon; Sulfur; Temperature; Thin films; United States > US

Figure 8 illustrates two explanations (a) and (b) of different memory erase sequences. Initially, figure 8(i), for erase, that is the return to the high resistance state, a current pulse about a factor of ten larger than the write pulse would have been applied to the device, localized in the crystallized column of the conducting device. If the leading edge rise time of the erase pulse is less than the thermal time constant of the device (>1 micro second) then all the energy from the erase pulse is initially dissipated in the crystal column and it melts. Immediately after that, the current of the conducting pulse can also expand into the glass surrounding the original conducting column towards an equilibrium molten filament state. In figure 8(ii) the material now consists of an inhomogeneous mixture of molten crystals and glass. As the period of time for which the erase pulse is applied increases, figure 8(iii), the concentration gradients around the regions of molten crystals provide the means, thermal diffusion, by which the material is returned to a homogeneous mixture. When this mixture is rapidly quenched, by the termination of the erase pulse, the material returns to its high resistance state, figure 8(iv), ready for the whole process to be repeated as necessary. For a single erase pulse the optimum length of time would be that required to return the material to the homogeneous state. The CNP model also provides an explanation of a common effect observed with devices that have been only "lightly" erased or had failed. It contains some words of caution for those proposing "soft" write or multilevel memory devices based on measurements of resistance. It deals with the subject of conduction by percolation. For particles of conducting material in an insulating matrix, with high conductivity ratios, there is a relatively smooth transition in the curve of electrical conductivity as a function of the volume fraction of conducting material. However, more important for field switching effects, the curve that describes the probability of a continuous path of conducting particles, becomes almost discontinuous at a volume fraction of 15 to 20%, as shown in figure 9. Which means that while a memory device may have a high two terminal resistance at low voltage there can still exist a very narrow diameter path of conducting particles between the electrodes. When voltage much less than the nominal threshold voltage is applied to such a device, it will switch. The conduction mechanisms in the glass will then allow a conducting filament to expand from that single column and grow to form the normal single filament of molten conducting material in the glass matrix. Even if the narrow conducting path has small gaps low voltage switching will bridge those gaps and allow the conducting filament to still grow and expand from the path. When subjected to read pulses, such a device will conduct and have a zero threshold voltage, even though outwardly it appears to be in the high resistance state it responds to low voltage as a low resistance device. First, consider a planar device with an amorphous film thickness of 1mm operating at room temperature with a switching threshold voltage of 10V. At a temperature of 125 degrees C the device will have a threshold voltage of 3V or 0V for a linear temperature coefficients of threshold voltage of 0.7%/degree C and 1%/degree C respectively. Such a device would be limited to operation at up to only 70 degrees C - if, however, there is a requirement to operate the device at an ambient temperature of 125 degrees C, with a junction temperature of 150 degrees C. In the example cited above, both threshold switching voltages would be <0V. Those simple calculations take no account of any guard-band required to deal with the statistics of manufacturing and operations, including reduction of threshold voltage with write/erase lifetime. Moving to low temperature operation, at -55 degrees C, the same device will have a threshold voltages of either 15.6V or 18V.