Comparison frequency doubling and charge pump matching techniques for dual-band Delta capital sigma fractional-N frequency synthesizer

• Published in: IEEE journal of solid-state circuits Vol. 40; no. 11
• Main Authors: Huh, Hyungki, Koo, Yido, Lee, Kang-Yoon, Ok, Yeonkyeong, Lee, Sungho, Kwon, Daehyun, Lee, Jeongwoo, Park, Joonbae, Lee, Kyeongho, Jeong, Deog-Kyoon, Kim, W
• Format: Journal Article
• Language: English
• Published: 01.01.2005
• Subjects: Channels; Charge pumps; Circuits; Compensation; Frequency synthesizers; Linearity; Noise; Offsets
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2005.857368

The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35- mu m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a Delta capital sigma modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.