Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT similar to 1 nm) SiO sub(2) and high- Kappa gate stacks

Building on a previously presented compact gate capacitance (C sub(g)-V sub(g)) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I sub(g)-V sub(g)) is provided for both ultrathin SiO sub(2) and high-dielectric constant (high...

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Published inIEEE transactions on electron devices Vol. 53; no. 5
Main Authors Fei Li, Fei Li, Mudanai, S P, Fan, Yang-Yu, Register, L F, Banerjee, S K
Format Journal Article
LanguageEnglish
Published 01.01.2006
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ISSN0018-9383
DOI10.1109/TED.2006.871877

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Summary:Building on a previously presented compact gate capacitance (C sub(g)-V sub(g)) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I sub(g)-V sub(g)) is provided for both ultrathin SiO sub(2) and high-dielectric constant (high- Kappa ) gate stacks of equivalent oxide thickness (EOT) down to similar to 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C sub(g)-V sub(g) model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schroedinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO sub(2) and high- Kappa /SiO sub(2) gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO sub(2), Si sub(3)N sub(4), and high- Kappa (e.g., HfO sub(2)) gate stacks on (100) Si with EOTs down to similar to 1-nm show excellent agreement.
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ISSN:0018-9383
DOI:10.1109/TED.2006.871877