A 3a8 GHz Delay-Locked Loop With Cycle Jitter Calibration

A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty c...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 55; no. 11
Main Authors Chuang, Chi-Nan, Liu, Shen-Iuan
Format Journal Article
LanguageEnglish
Published 01.01.2008
Subjects
Calibration
Circuits
CMOS
Dividers
Dynamic link libraries
Electric potential
Jitter
Voltage
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Summary:A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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ISSN:1549-7747
DOI:10.1109/TCSII.2008.2002561